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MC74HC4020ADR2G

  

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ON-Semiconductor
ON Semiconductor
MC74HC4020ADR2G 14−Stage Binary Ripple Counter

14−Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4020ADG  MC74HC4020ADR2_05  MC74HC4020ADTR2G  MC74HC4020ADTR2_05  MC74HC4020AD_05  MC74HC4020AF  MC74HC4020AFEL  MC74HC4020AFELG  MC74HC4020AFG  MC74HC4020ANG  
MC74HC4020ADR2G PDF
ONSEMI
ON Semiconductor
MC74HC4020ADR2G 14−Stage Binary Ripple Counter

14−Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4020A  MC74HC4020AN  MC74HC4020ANG  MC74HC4020AD  MC74HC4020ADG  MC74HC4020ADR2  MC74HC4020ADTR2  MC74HC4020ADTR2G  MC74HC4020AF  MC74HC4020AFG  
MC74HC4020ADR2G PDF
ON-Semiconductor
ON Semiconductor
MC74HC4020ADR2G_11 14-Stage Binary Ripple Counter

14-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant


other parts : MC74HC4020A_11  MC74HC4020ANG_11  MC74HC4020ADG_11  MC74HC4020ADTR2G_11  MC74HC4020AFG_11  MC74HC4020AFELG_11  
MC74HC4020ADR2G_11 PDF
ON-Semiconductor
ON Semiconductor
MC74HC4020ADR2G_14 14-Stage Binary Ripple Counter

14-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
   Compliant


other parts : MC74HC4020A_14  MC74HC4020ADG_14  MC74HC4020ADTR2G_14  NLV74HC4020ADTR2G_14  
MC74HC4020ADR2G_14 PDF
ON-Semiconductor
ON Semiconductor
MC74HC4020ADR2G_10 14-Stage Binary Ripple Counter

14-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available


other parts : MC74HC4020A_10  MC74HC4020AN_10  MC74HC4020ANG_10  MC74HC4020AD_10  MC74HC4020ADG_10  MC74HC4020ADR2_10  MC74HC4020ADTR2_10  MC74HC4020ADTR2G_10  MC74HC4020AF_10  MC74HC4020AFG_10  
MC74HC4020ADR2G_10 PDF

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