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MC74HC4040A

  

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ONSEMI
ON Semiconductor
MC74HC4040A 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant


other parts : MC74HC4040ADG  MC74HC4040ADR2G  NLV74HC4040ADR2G  MC74HC4040ADTR2G  
MC74HC4040A PDF
Motorola
Motorola => Freescale
MC74HC4040A 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS

The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates


other parts : MC54HC4040A  MC54HC4040AJ  MC74AC4040D  MC74AC4040N  MC74HC4040AD  MC74HC4040ADT  MC74HC4040AN  
MC74HC4040A PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040A 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant


other parts : MC74HC4040ADG  MC74HC4040ADR2G  MC74HC4040ADTR2G  MC74HC4040A_14  NLV74HC4040ADR2G  
MC74HC4040A PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040AD 12−Stage Binary Ripple Counter

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4040A_05  MC74HC4040AN  MC74HC4040ANG  MC74HC4040ADR2  MC74HC4040ADTR2  MC74HC4040AF  MC74HC4040AFG  MC74HC4040AFEL  MC74HC4040AFELG  
MC74HC4040AD PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040AN 12−Stage Binary Ripple Counter

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4040A_05  MC74HC4040ANG  MC74HC4040AD  MC74HC4040ADR2  MC74HC4040ADTR2  MC74HC4040AF  MC74HC4040AFG  MC74HC4040AFEL  MC74HC4040AFELG  
MC74HC4040AN PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040AF 12−Stage Binary Ripple Counter

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4040A_05  MC74HC4040AN  MC74HC4040ANG  MC74HC4040AD  MC74HC4040ADR2  MC74HC4040ADTR2  MC74HC4040AFG  MC74HC4040AFEL  MC74HC4040AFELG  
MC74HC4040AF PDF
Motorola
Motorola => Freescale
MC74HC4040AD 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS

The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates


other parts : MC54HC4040A  MC54HC4040AJ  MC74AC4040D  MC74AC4040N  MC74HC4040A  MC74HC4040ADT  MC74HC4040AN  
MC74HC4040AD PDF
Motorola
Motorola => Freescale
MC74HC4040AN 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS

The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates


other parts : MC54HC4040A  MC54HC4040AJ  MC74AC4040D  MC74AC4040N  MC74HC4040A  MC74HC4040AD  MC74HC4040ADT  
MC74HC4040AN PDF
ONSEMI
ON Semiconductor
MC74HC4040ADG 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High−Performance Silicon−Gate CMOS

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant


other parts : MC74HC4040A  MC74HC4040ADR2G  NLV74HC4040ADR2G  MC74HC4040ADTR2G  
MC74HC4040ADG PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040ADT 12−Stage Binary Ripple Counter

12−Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates


other parts : MC74HC4040ADR2_00  MC74HC4040ADTEL  MC74HC4040ADTR2_00  MC74HC4040AD_00  MC74HC4040AFL1  MC74HC4040AFR1  MC74HC4040AFR2  MC74HC4040AN_00  MC74HC4040A_00  MC74HC4040  
MC74HC4040ADT PDF
ON-Semiconductor
ON Semiconductor
MC74HC4040AFG 12−Stage Binary Ripple Counter

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*


other parts : MC74HC4040A_05  MC74HC4040AN  MC74HC4040ANG  MC74HC4040AD  MC74HC4040ADR2  MC74HC4040ADTR2  MC74HC4040AF  MC74HC4040AFEL  MC74HC4040AFELG  
MC74HC4040AFG PDF
Motorola
Motorola => Freescale
MC74HC4040ADT 12-Stage Binary Ripple Counter

12-Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS

The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates


other parts : MC54HC4040A  MC54HC4040AJ  MC74AC4040D  MC74AC4040N  MC74HC4040A  MC74HC4040AD  MC74HC4040AN  
MC74HC4040ADT PDF

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